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Communications Processor (CP)
Characters are included in the block check sequence (BCS) calculation on a per-buffer ba-
sis. Each buffer can be independently programmed to be included or excluded from the BCS
calculation, and any characters to be excluded from the BCS calculation must reside in a
separate buffer. The BISYNC controller can reset the BCS generator before transmitting a
specific buffer. When functioning in transparent mode, the BISYNC controller automatically
inserts a DLE before transmitting a DLE character. In this case, only one DLE is used in the
calculation of the BCS.
The IMP may also be used to transmit characters in a promiscuous (totally transparent)
mode. See 4.5.16 Transparent Controller.
4.5.13.2 Bisync Channel Frame Reception Processing
Although the BISYNC receiver is designed to work with almost no intervention from the
M68000 core, it allows user intervention on a per-byte basis if necessary. The BISYNC re-
ceiver can perform CRC16, longitudinal redundancy check (LRC), or vertical redundancy
check (VRC) checking, SYNC stripping in normal mode, DLE-SYNC stripping and stripping
of the first DLE in DLE-DLE pairs in transparent mode, and control character recognition. A
control character is one belonging to the control characters shown in Figure 4-31.
When the M68000 core enables the BISYNC receiver, it will enter hunt mode. In this mode,
as data is shifted into the receiver shift register one bit at a time, the contents of the register
are compared to the contents of the SYN1–SYN2 fields in the data synchronization register.
If the two are not equal, the next bit is shifted in, and the comparison is repeated. When the
registers match, the hunt mode is terminated, and character assembly begins. The BISYNC
controller is now character synchronized and will perform SYNC stripping and message re-
ception. The BISYNC controller will revert to the hunt mode when it is issued the ENTER
HUNT MODE command, upon recognition of some error condition, or upon reception of an
appropriately defined control character.
When receiving data, the BISYNC controller updates the BCS bit (CR) in the BD for every
byte transferred. When the data buffer has been filled, the BISYNC controller clears the
empty (E) bit in the BD and generates an interrupt if the interrupt (I) bit in the BD is set. If the
incoming data exceeds the length of the data buffer, the BISYNC controller will fetch the next
BD in the table and, if it is empty, will continue to transfer data to this BD's associated data
buffer.
When a BCS is received, it is checked and written to the data buffer. The BISYNC controller
sets the last bit, writes the message status bits into the BD, and clears the empty bit. Then
it generates a maskable interrupt, indicating that a block of data has been received and is in
memory. Note that the SYNC in the nontransparent mode or DLE-SYNC pairs in the trans-
parent mode (i.e., an underrun condition) are not included in the BCS calculations.
The IMP may also be used to receive characters in a promiscuous (totally transparent)
mode. See 4.5.16 Transparent Controller.
4.5.13.3 Bisync Memory Map
When configured to operate in BISYNC mode, the IMP overlays the structure listed in Table
4-8 onto the protocol-specific area of that SCC parameter RAM. Refer to 2.8 MC68302
MOTOROLA
MC68302 USER'S MANUAL
4-85
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