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Communications Processor (CP)
TX—Tx Buffer
A buffer has been transmitted. If the L bit in the Tx BD is set, TX is set no sooner than on
the second-to-last bit of the last byte being transmitted on the TXD pin. If the L bit in the
Tx BD is cleared, TX is set after the last byte was written to the transmit FIFO.
RX—Rx Buffer
A complete buffer has been received on the transparent channel. RX is set no sooner than
10 serial clocks after the last bit of the last byte in the buffer is received on the RXD pin.
4.5.16.11 Transparent Mask Register
The SCC mask register (SCCM) is referred to as the transparent mask register when the
SCC is operating as a transparent controller. It is an 8-bit read-write register that has the
same bit format as the transparent event register. If a bit in the transparent mask register is
a one, the corresponding interrupt in the event register will be enabled. If the bit is zero, the
corresponding interrupt in the event register will be masked. This register is cleared at reset.
4.6 SERIAL COMMUNICATION PORT (SCP)
The SCP (see Figure 4-44) is a full-duplex, synchronous, character-oriented channel that
provides a three-wire interface (receive, transmit, and clock). The SCP consists of indepen-
dent transmitter and receiver sections and a common clock generator. The transmitter and
receiver sections use the same clock, which is derived from the main clock by a separate
on-chip baud rate generator. Since the MC68302 is an SCP master for this serial channel,
it generates both the enable and the clock signals.
The SCP allows the MC68302 to exchange status and control information with a variety of
serial devices, using a subset of the Motorola serial peripheral interface (SPI). The SCP is
compatible with SPI slave devices. These devices include industry-standard CODECs as
well as other microcontrollers and peripherals.
The SCP enable signals, which can be implemented using the general-purpose I/O pins, are
used to enable one of several potential SCP slave devices. The clock signal (SPCLK) shifts
the received data (SPRXD) in and shifts the transmitted data (SPTXD) out. The clock is gat-
ed; it operates only while data is being transferred and is idle otherwise.
Two successive byte transmissions over the SCP cannot occur immediately back-to-back.
A minimum delay of two to eight bit times is imposed by the SCP, depending on the SCP
clock rate (Communication processor priorities and software handling of interrupts may con-
tribute extra delays). Higher SCP clock rates give higher minimum delay.
4-134
MC68302 USER'S MANUAL
MOTOROLA
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