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The IDL bus connects one IDL master to one or more IDL slaves. The IDL bus timing is driv-
en by the master device.
The bus signals are as follows:
• CLOCK — always provided from the master to the slave. It provides the bit timing for
the data traveling across the IDL.
• SYNC —provides the framing for the IDL. The SYNC occurs once per 125- sec frame
and is active high one full clock cycle in the bit immediately preceding the data transac-
tion.
• TXDATA — drives the data from one chip to another. The line is in high impedance
when no data transaction occurs.
• RXDATA — the input line that receives data from the TXDATA of another part.
D.6.6 IMP/IDL Interconnection
The MC68302 directly connects to the IDL bus with no glue logic. The MC68302 is an IDL
slave (accepts IDL timing from the bus). In the application described, the IDL master device
is the MC145475 S/T interface chip (see Figure D-14).
CLOCK
SYNC
TXDATA
RXDATA
MOTOROLA
B1
D
A
D
A
B1
Figure D-13. IDL Frame Structure
MC68302 USER'S MANUAL
D
M
B2
D
M
B2
MC68302 Applications
D-33
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