Masking Interrupt Sources And Events - Motorola MC68302 User Manual

System Integration Block (SIB)
requests, if any, are then assessed by priority so that another interrupt request may be
presented to the core.
2. The 3-bit mask in the M68000 core status register (SR) ensures that a subsequent in-
terrupt request at a higher interrupt priority level will suspend handling of a lower pri-
ority interrupt. The 3-bit mask indicates the current M68000 priority. Interrupts are in-
hibited for all priority levels less than or equal to the current M68000 priority. Priority
level 7 cannot be inhibited by the mask; it is a nonmaskable interrupt level.
3. The interrupt controller allows a higher priority INRQ interrupt to be presented to the
M68000 core before the servicing of a lower priority INRQ interrupt is completed. This
is achieved using the interrupt in-service register (ISR). Each bit in the ISR corre-
sponds to an INRQ interrupt source.
4. During an interrupt acknowledge cycle for an INRQ interrupt, the in–service bit is set
by the interrupt controller for that interrupt source. When this bit is set, any subsequent
INRQ interrupt requests at this priority level or lower are disabled until servicing of the
current interrupt is completed and the in-service bit is cleared by the user. Pending in-
terrupts for these sources are still set by the corresponding interrupt pending bit.
5. Thus, in the interrupt service routine for the INRQ interrupt, the user can lower the
M68000 core mask to level 3 in the status register to allow higher priority level 4 (IN-
RQ) interrupts to generate an interrupt request. This capability provides nesting of
INRQ interrupt requests for sources within level 4. This capability is similar to the way
the M68000 core interrupt mask provides nesting of interrupt requests for the seven
interrupt priority levels.

3.2.3 Masking Interrupt Sources and Events

The user may mask EXRQ and INRQ interrupts to prevent an interrupt request to the
M68000 core. EXRQ interrupt masking is handled external to the IMP—e.g., by program-
ming a mask register within an external device. INRQ interrupt masking is accomplished by
programming the IMR. Each bit in the IMR corresponds to one of 15 INRQ interrupt sources.
When a masked INRQ interrupt source has a pending interrupt request, the corresponding
bit is set in the IPR, even though the interrupt is not generated to the core. By masking all
interrupt sources using the IMR, the user may implement a polling interrupt servicing
scheme for INRQ interrupts, as discussed in 3.2.5.2 Interrupt Pending Register (IPR).
When an INRQ interrupt source from an on-chip peripheral has multiple interrupt events, the
user can individually mask these events by programming that peripheral's mask register
(see Figure 3-3). Table 3-4 indicates the interrupt sources that have multiple interrupt
events. In this case, when a masked event occurs, an interrupt request is not generated for
the associated interrupt source, and the corresponding bit in the IPR is not set. If the corre-
sponding bit in the IPR is already set, then masking the event in the peripheral mask register
causes the IPR bit to be cleared. To determine the cause of a pending interrupt when an
interrupt source has multiple interrupt events, the user interrupt service routine must read
the event register within that on-chip peripheral. By clearing all unmasked bits in the event
register, the IPR bit is also cleared.
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