Ddcmp Programming Model; Ddcmp Command Set; Table 4-10. Ddcmp Specific Parameter Ram - Motorola MC68302 User Manual

Communications Processor (CP)
Address
SCC Base + 9C
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2
SCC Base + A4 #
SCC Base + A5 #
SCC Base + A6
SCC Base + A7 #
SCC Base + A8
SCC Base + A9 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE #
SCC Base + B0 #
SCC Base + B2
SCC Base + B4
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
# Initialized by the user (M68000 core).

4.5.14.4 DDCMP Programming Model

The M68000 core configures each SCC to operate in one of four protocols by the MODE1–
MODE0 bits in the SCC mode register. If MODE1–MODE0 = 10, DDCMP operation is se-
lected with synchronous links. For asynchronous links, MODE1–MODE0 = 01 (ASYNC)
should be selected, and the DDCMP bit in the UART mode register should be set. The
SYN1–SYN2 synchronization characters are programmed in the data synchronization reg-
ister (DSR). See 4.5.4 SCC Data Synchronization Register (DSR) for more programming in-
formation. The DDCMP controller uses the same basic data structure as the UART, HDLC,
and BISYNC controllers.
The DDCMP controller generates and checks the CRC16 message trailer. It can be preset
to ones or zeros by writing to the preset CRC (PCRC) register before enabling the receiver
or the transmitter. The received message length (RMLG) is the header byte count value as
determined by the receiver, and the received message length counter (RMLG _ CNT) is the
temporary received data downcounter.
Receive and transmit errors are reported in their respective BDs. The line status signals (CD
and CTS) may be read in the SCC status register and a maskable interrupt is generated
upon each status change (see 4.5.2 SCC Configuration Register (SCON)).

4.5.14.5 DDCMP Command Set.

The following commands are issued to the command register:
STOP TRANSMIT Command
After a hardware or software reset and the enabling of the channel in the SCC mode reg-
ister, the channel is in the transmit enable mode and starts polling the first BD in the table
approximately every eight transmit clocks.
The channel STOP TRANSMIT command disables the transmission of messages on the
transmit channel. If this command is received by the DDCMP controller during message
4-104

Table 4-10. DDCMP Specific Parameter RAM

Name
RCRC
CRCC
PCRC
TCRC
DSYN1
DSOH
Reserved
DENQ
Reserved
DDLE
CRC1EC
CRC2EC
NMARC
DISMC
RMLG
RMLG_CNT
DMASK
DADDR1
DADDR2
DADDR3
DADDR4
MC68302 USER'S MANUAL
Width
Word Temp Receive CRC
Word CRC16 Constant
Word Preset CRC16
Word Temp Transmit CRC
Byte DDCMP SYN1 Character
Byte DDCMP SOH Character
Byte
Byte DDCMP ENQ Character
Byte
Byte DDCMP DLE Character
Word CRC1 Error Counter
Word CRC2 Error Counter
Word Nonmatching Address Received Counter
Word Discard Message Counter
Word Received Message Length
Word Received Message Length Counter
Word User-Defined Frame Address Mask
Word User-Defined Frame Address
Word User-Defined Frame Address
Word User-Defined Frame Address
Word User-Defined Frame Address
Description
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