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Signal Description
Chip Select
Testing
V DD
GND
All pins except EXTAL, CLKO, and the layer 1 interface pins in IDL mode support TTL levels.
EXTAL, when used as an input clock, needs a CMOS level. CLKO supplies a CMOS level
output. The IDL interface is specified as a CMOS electrical interface.
All outputs (except CLKO and the GCI pins) drive 130 pF. CLKO is designed to drive 50 pF.
The GCI output pins drive 150 pF.
5.2 POWER PINS
The IMP has 21 power supply pins. Careful attention has been paid to reducing IMP noise,
potential crosstalk, and RF radiation from the output drivers. Inputs may be +5 V when V
is 0 V without damaging the device.
• V
(8)—There are 8 power pins.
DD
• GND (13)—There are 13 ground pins.
The Input High Voltage and Input Low Voltage for EXTAL and
the values for power are specified in the DC Electrical Charac-
teristics.A valid clock signal oscillates between a low voltage of
between V
and V
DD
after V
5-2
Table 5-1. Signal Definitions
CS3–CS0
FRZ (2 Spare)
-0.3 and .6 volts and a high voltage of between 4.0
SS
volts. This EXTAL signal must be present within 20 mS
reaches its minimum specified level of 4.5 volts.
DD
MC68302 USER'S MANUAL
NOTE
4
3
8
13
DD
MOTOROLA
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