Motorola MC68302 User Manual page 401

MC68302 Applications
of the physical interface configuration. Similarly, all bits in the receive buffer will be filled with
real transparent data (full packing is always performed), regardless of the physical interface
configuration.
If no data is available to transmit, transparent mode will transmit ones. The decision of
whether to set the last (L) bit in the Tx BD is left to the user. If multiple buffers are to be sent
back-to-back with no gaps in between, the L bit should be cleared in all buffers except for
the last buffer. In this case, failure to provide buffers in time will result in a transmit underrun.
If the L bit is set, the frame will end without error, and the transmission of ones will resume.
The transmit byte count and buffer alignment need not be even, but the SDMA channel will
always read words on an even-byte boundary, even if it has to discard one of the two bytes.
For example, if a transmit buffer begins on an odd-byte boundary and is 10 bytes in length
(worst case), six word reads will result, even though only 10 bytes will be transmitted.
The receive buffer length (stored in MRBLR) and starting address must be even. All trans-
fers to memory will be of word length and, unless an error occurs, a buffer will not be closed
until it contains MRBLR/two words (the byte count will be equal to MRBLR). This raises an
important point. Data received will only be transmitted to memory every 16 clocks. If a non-
multiple of 16 bits is sent in a frame, the residue bits will not be transmitted to memory until
additional bits arrive, and it will be impossible to demarcate frames unless their length is pre-
determined. (If a SYNC character is received with the data, the BISYNC mode can be used
to receive an odd number of bytes with odd-length receive buffers and pointers allowed. (For
more detailed information, refer to D.8.6 Other NMSI Modes.)
When the enable transmitter (ENT) bit is set, the process of polling the Tx BD begins by the
RISC. The frequency of this polling is determined by the SCC's transmit clock. If the clock
is stopped, no polling will occur. When the ready bit of the first Tx BD is set, the RISC ini-
tiates the SDMA activity of filling up the transmit FIFO with three words of data. Once the
FIFO is full, the RTS signal is asserted, and the physical interface signals take control to de-
termine the exact timing of the transmitted data. Once the physical interface says "go", typ-
ically one final $FF is transmitted before data begins; however, whether $FF is transmitted
depends on the mode chosen.
When the enable receiver (ENR) bit is set and 16 bits of valid data (as defined by the phys-
ical interface signals) have been clocked into the receiver, the RISC checks to see if the first
receive buffer is available and, if the buffer is available, begins moving the data to it. The
receive FIFO is three words deep, but a single open entry in the FIFO causes an SDMA ser-
vice request. There are three types of receive errors: overrun (receive FIFO overflow), busy
(new data arrived without a receive buffer being available), and CD lost (which is not possi-
ble in any example configuration discussed in this appendix). These errors are reported in
the SCC event register (SCCE) or the Rx BD.
Whenever a buffer has been transmitted with the interrupt (I) bit set in the Tx BD, the TX
event in the SCCE register will be set. This TX bit can cause an interrupt if the corresponding
bit in the SCCM is set. Similarly, whenever a buffer has been received with the interrupt (I)
bit set in the Rx BD, the RX event in the SCCE register will be set. Also, whenever a word
of data is written to the receive buffer, the RCH bit is set in the SCCE.
MOTOROLA MC68302 USER'S MANUAL D-51