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TX—Tx Buffer
0 = No interrupt.
1 = A buffer has been transmitted on the UART channel (set only if the I bit in the Tx
buffer descriptor is set).
RX—Rx Buffer
0 = No interrupt.
1 = A buffer was received on the UART channel (set only if the I bit in the Rx buffer
descriptor is set).
E.2.1.2.5 UART Mask Register (SCCM). This 8-bit register is located at offset $88A
(SCC1), $89A (SCC2), and $8AA (SCC3) on D15-D8 of a 16-bit data bus. The SCCM is
used to enable and disable interrupt events reported by the SCCE. The mask bits corre-
spond to the interrupt event bit shown in the SCCE. A bit should be set to one to enable the
corresponding interrupt in the SCCE.
E.2.1.2.6 UART Status Register (SCCS). This 8-bit register is located at offset $88C
(SCC1), $89C (SCC2), and $8AC (SCC3), on D15-D8 of a 16-bit data bus. The SCCS reg-
ister reflects the current status of the RXD, CD, and CTS lines as seen by the SCC.
ID—Idle Status on the Receiver Line (valid only when the ENR bit is set and the receive
clock is running)
0 = Receiver Line is not idling.
1 = Either CD is not asserted or the receiver line is idling while CD is asserted.
CD—Carrier Detect Status Changed (valid only when the ENR bit is set and the receive
clock is running)
0 = CD is asserted.
1 = CD is not asserted.
CTS—Clear-To-Send Status Changed (valid only when the ENT bit is set and the transmit
clock is running)
0 = CTS is asserted.
1 = CTS is not asserted.
E.2.1.3 GENERAL AND UART PROTOCOL-SPECIFIC PARAMETER RAM. Each SCC
has 32 words of parameter RAM used to configure receive and transmit operation, store
temporary parameters for the CP, and maintain counters. The first 14 words are general
parameters, which are the same for each protocol. The last 18 words are specific to the pro-
tocol selected. The following sections discuss the parameters that the user must initialize to
configure the UART operation.
MOTOROLA
7
6
5
4
CTS
CD
IDL
BRK
7
6
5
4
—
—
—
—
MC68360 USER'S MANUAL
SCC Programming Reference
3
2
1
0
CCR
BSY
TX
RX
3
2
1
0
—
ID
CD
CTS
E-23
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