Table of Contents
Advertisement
Table 5-3. Bus Signal Summary—IDMA and SDMA
Signal Name
A23–A1, FC–FC0,
AS, UDS, LDS, R/W, RMC
BCLR
IAC
D15—D0 Read
D15—D0 Write
DTACK
BR
BG
BGACK
HALT
RESET
BERR
**
If DTACK is generated automatically (internally) by the chip-select logic, then it is an output. Otherwise, it is an
input.
***
BERR is an open-drain output, and may be asserted by the IMP when the hardware watchdog is used or when
the chip-select logic detects address conflict or write protect violation. BERR may be asserted by external logic in
all cases.
# Applies to disable CPU mode only. The internal signal IBCLR is used otherwise.
## Applies to disable CPU mode only, otherwise N/A.
5.11 PHYSICAL LAYER SERIAL INTERFACE PINS
The physical layer serial interface has 24 pins, and all but one of them have multiple func-
tionality. The pins can be used in a variety of configurations in ISDN or non-ISDN environ-
ments. Table 5-3 shows the functionality of each group of pins and their internal connection
to the three SCC and one SCP controllers. The physical layer serial interface can be config-
ured for non-multiplexed operation (NMSI) or multiplexed operation that includes IDL, GCI,
and PCM highway modes. IDL and GCI are ISDN interfaces. When working in one of the
multiplexed modes, the NMSI1/ISDN physical interface can be connected to all three SCC
controllers.
First Function
NMSI1 (8)
NMSI2 (8)
NMSI3 (5)
NMSI3 (3)
NOTE: Each one of the parallel I/O pins can be configured individually.
MOTOROLA
Internal
Pin Type
Memory
Space
I/O
I/O Open Drain
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O Open Drain
I/O Open Drain
I/O Open Drain
Table 5-4. Serial Interface Pin Functions
Connected To
SCC1 Controller
SCC2 Controller
SCC3 Controller
SCC3 Controller
MC68302 USER'S MANUAL
IDMA Master
Access To
External
Memory
Space
O
O
I #
I #
O
O
O
I
O
O
**
O
O ##
O ##
I ##
I ##
O
O
I
I
I
I
***
***
I/O
I/O
Second Function
ISDN Interface
PIO—Port A
PIO—Port A
SCP
Signal Description
SDMA Master
Access To
Internal
External
Memory
Memory
Space
Space
N/A
O
N/A
O
N/A
O
N/A
I
N/A
O
**
N/A
N/A
O ##
N/A
I ##
N/A
O
N/A
I
N/A
I
***
N/A
I/O
Connected To
SCC1/SCC2/SCC3
Parallel I/O
Parallel I/O
SCP Controller
5-13
Advertisement
Table of Contents
