Disable Cpu Logic (M68000) - Motorola MC68302 User Manual

System Integration Block (SIB)
After system reset, this bit defaults to zero. If BCLM is set, then the typical maximum inter-
rupt latency is about 78 clocks in a zero-wait-state system. This assumes a standard instruc-
tion mix, that the IDMA is just beginning a four-bus-cycle transfer when the interrupt
becomes pending, and that an SDMA has an access pending (one bus cycle). Interrupt ex-
ecution time is 44 clocks and includes the time to execute the interrupt acknowledge cycle,
save the status register and PC value on the stack, and then vector to the first location of
the interrupt service routine. Thus, the calculation is 78 = 14 (instruction completion) + 20
(DMAs) + 44 (interrupt execution).
SDMA operation is not affected by the BCLM bit. Note that the SDMA accesses only one
byte/word of external memory at a time before giving up the bus and that accesses are rel-
atively infrequent. External bus master operation may or may not be affected by the BCLM
bit, depending on whether the BCLR signal is used to clear the external master off the bus.
Without using the BCLM bit, the maximum interrupt latency includes the maximum time that
the IDMA or external bus master could use the bus in the worst case. Note that the IDMA
can limit its bus usage if its requests are generated internally.
The IPA status bit will be set, regardless of the BCLM value.
SAM—Synchronous Access Mode
This bit controls how external masters may access the MC68302 peripheral area. This bit
is not relevant for applications that do not have external bus masters that access the
MC68302. In applications such as disable CPU mode, in which the M68000 core is not
operating, the user should note that SAM may be changed by an external master on the
first access of the MC68302, but that first write access must be asynchronous with three
wait states. (If DTACK is used to terminate bus cycles, this change need not influence
hardware.)
0 = Asynchronous accesses. All accesses to the MC68302 internal RAM and registers
(including BAR and SCR) by an external master are asynchronous to the MC68302
clock. Read and write accesses are with three wait states, and DTACK is asserted
by the MC68302 assuming three wait-state accesses. This is the default value.
1 = Synchronous accesses. All accesses to the MC68302 internal RAM and registers
(including BAR and SCR) must be synchronous to the MC68302 clock. Synchro-
nous read accesses may occur with one wait state if EMWS is also set to one.

3.8.4 Disable CPU Logic (M68000)

The MC68302 can be configured to operate solely as a peripheral to an external processor.
In this mode, the on-chip M68000 CPU should be disabled by strapping DISCPU high during
system reset (RESET and HALT asserted simultaneously). The internal accesses to the
MC68302 peripherals and memory may be asynchronous or synchronous. During synchro-
nous reads, one wait state may be used if required (EMWS bit set). The following pins
change their functionality in this mode:
1. BR will be an output from the IDMA and SDMA to the external M68000 bus, rather than
being an input to the MC68302.
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NOTE
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