Hdlc Memory Map; Hdlc Programming Model; Table 4-8. Hdlc-Specific Parameter Ram - Motorola MC68302 User Manual

ceeds the length of the data buffer, the HDLC controller will fetch the next BD in the table
and, if it is empty, will continue to transfer the rest of the frame to this BD's associated data
buffer.
During this process, the HDLC controller will check for a frame that is too long. When the
frame ends, the CRC field is checked against the recalculated value and is written to the
data buffer starting with the first address byte. The data length written to the last BD in the
HDLC frame is the length of the entire frame. This enables HDLC protocols that "lose"
frames to correctly recognize the frame-too-long condition. The HDLC controller then sets
the last buffer in frame bit, writes the frame status bits into the BD, and clears the empty bit.
The HDLC controller next generates a maskable interrupt, indicating that a frame has been
received and is in memory. The HDLC controller then waits for a new frame. Back-to-back
frames may be received with only a single shared flag between frames. Also, flags that
share a zero will be recognized as two consecutive flags.

4.5.12.3 HDLC Memory Map

When configured to operate in HDLC mode, the IMP overlays the structure shown in Table
4-7 onto the protocol-specific area of that SCC parameter RAM. Refer to 2.8 MC68302
Memory Map for the placement of the three SCC parameter RAM areas and to Table 4-2 for
the other parameter RAM values.
Address
SCC Base + 9C
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2 #
SCC Base + A4
SCC Base + A6
SCC Base + A8 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE #
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
# Initialized by the user (M68000 core).
An incorrect initialization of C_MASK may be used to "force" re-
ceive CRC errors for software testing purposes. The transmit
CRC will not be affected.

4.5.12.4 HDLC Programming Model

The M68000 core configures each SCC to operate in one of four protocols by the MODE1–
MODE0 bits in the SCC mode register (SCM). MODE1–MODE0 = 00 selects HDLC mode.
MOTOROLA

Table 4-8. HDLC-Specific Parameter RAM

Name Width
RCRC_L Word
RCRC_H Word
C_MASK_L Word
C_MASK_H Word
TCRC_L Word
TCRC_H Word
DISFC Word
CRCEC Word
ABTSC Word
NMARC Word
RETRC Word
MFLR Word
MAX_cnt Word
HMASK Word
HADDR1 Word
HADDR2 Word
HADDR3 Word
HADDR4 Word
MC68302 USER'S MANUAL
Communications Processor (CP)
Temp Receive CRC Low
Temp Receive CRC High
Constant ($F0B8 16-Bit CRC, $DEBB 32-Bit CRC)
Constant ($XXXX 16-Bit CRC, $20E3 32-Bit CRC)
Temp Transmit CRC Low
Temp Transmit CRC High
Discard Frame Counter
CRC Error Counter
Abort Sequence Counter
Nonmatching Address Received Counter
Frame Retransmission Counter
Max Frame Length Register
Max_Length Counter
User-Defined Frame Address Mask
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
NOTE
Description
4-69