Mc68302 Imp Configuration Control; Figure 2-5. Mc68302 Imp Configuration Control - Motorola MC68302 User Manual

MC68000/MC68008 Core

2.7 MC68302 IMP CONFIGURATION CONTROL

Four reserved entries in the external M68000 exception vector table (see Table 2-5) are
used as addresses for internal system configuration registers. These entries are at locations
$0F0, $0F4, $0F8, and $0FC. The first entry is the on-chip peripheral base address register
(BAR) entry; the second is the on-chip system control register (SCR) entry; the least signif-
icant word of the third entry is the clock control register (CKCR), and fourth entry is reserved
for future use.
The BAR entry contains the BAR described in this section. The SCR entry contains the SCR
described in 3.8.1 System Control Register (SCR). The CKCR entry contains the CKCR reg-
ister described in 3.9 Clock Control Register.
Figure 2-5 shows all the MC68302 IMP on-chip addressable locations and how they are
mapped into system memory.
BASE + $0
BASE + $400
BASE + $800
BASE + $FFF

Figure 2-5. MC68302 IMP Configuration Control

The on-chip peripherals, including those peripherals in both the CP and SIB, require a 4K-
byte block of address space. This 4K-byte block location is determined by writing the intend-
ed base address to the BAR in supervisor data space (FC = 5). The address of the BAR en-
2-12
MC68302
$0F0 BAR ENTRY
$0F4 SCR ENTRY
$0F8
CKCR ENTRY
$0FC
RESERVED
4K BLOCK
SYSTEM RAM
(DUAL-PORT)
PARAMETER RAM
(DUAL-PORT)
INTERNAL
REGISTERS
MC68302 USER'S MANUAL
SYSTEM MEMORY MAP
$0
EXCEPTION
VECTOR
TABLE
256 VECTOR
ENTRIES
$3FF
BAR
POINTS
TO THE
BASE
$xxx000 = BASE
4K BLOCK
$FFFFFF
MOTOROLA