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Communications Processor (CP)
If this bit is cleared, the BISYNC controller will look for the SYN1–SYN2 sequence in the
data synchronization register.
NTSYN—No Transmit SYNC
When this bit is set, the SCC operates in a promiscuous, totally transparent mode. See
4.5.16 Transparent Controller for details.
REVD—Reverse DATA
When this bit is set, the receiver and transmitter will reverse the character bit order, trans-
mitting the most significant bit first. This bit is valid in promiscuous mode.
BCS—Block Check Sequence
0 = LRC
For even LRC, the PRCRC and PTCRC preset registers in the BISYNC-specific
parameter RAM should be initialized to zero before the channel is enabled. For odd
LRC, the PRCRC and PTCRC registers should be initialized to ones. The LRC is
formed by the Exclusive OR of each 7-bits of data (not including synchronization
characters), and the parity bit is added after the final LRC calculation.
The receiver will check character parity when BCS is programmed to LRC and the
receiver is not in transparent mode. The transmitter will transmit character parity
when BCS is programmed to LRC and the transmitter is not in transparent mode.
Use of parity in BISYNC assumes the use of 7-bit data characters.
1 = CRC16
The PRCRC and PTCRC preset registers should be initialized to a preset value of
all zeros or all ones before the channel is enabled. In both cases, the transmitter
sends the calculated CRC non-inverted, and the receiver checks the CRC against
zero. Eight-bit characters (without parity) are configured when CRC16 is chosen.
The CRC16 polynomial is as follows:
Bit 10—Reserved for future use.
RTR—Receiver Transparent Mode
0 = The receiver is placed in normal mode with SYNC stripping and control character
recognition operative.
1 = The receiver is placed in transparent mode. SYNCs, DLEs, and control characters
are only recognized after a leading DLE character. The receiver will calculate the
CRC16 sequence, even if programmed to LRC while in transparent mode. PRCRC
should be first initialized to the CRC16 preset value before setting this bit.
RBCS—Receive Block Check Sequence
The BISYNC receiver internally stores two BCS calculations with a byte delay (eight serial
clocks) between them. This enables the user to examine a received data byte and then
decide whether or not it should be part of the BCS calculation. This is useful when control
4-92
X 16 + X 15 + X 2 + 1
MC68302 USER'S MANUAL
MOTOROLA
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