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WPV will be set, regardless of the value of WPVE.
RMCST—RMC Cycle Special Treatment
0 = The locked read-modify-write cycles of the TAS instruction will be identical to the
M68000 (AS and CS will be asserted during the entire cycle). The arbiter will issue
BG, regardless of the M68000 core RMC. If an IMP chip select is used, the DTACK
generator will insert wait states on the read cycle only.
1 = The MC68302 uses RMC to negate AS and CS at the end of the read portion of
the RMC cycle and reasserts AS and CS at the beginning of the write portion. BG
will not be asserted until the end of the write portion. If an IMP chip select is used,
the DTACK generator will insert wait states on both the read and write portion of
the cycles.
The assertion of the RMC by the M68000 core is seen by the arbiter and will prevent the
arbiter from issuing bus grants until the completion of M68000-initiated locked read-mod-
ify-write activity. After system reset, this bit defaults to zero.
EMWS—External Master Wait State (EMWS);
When EMWS is set and an external master is using the chip-select logic for DTACK gen-
eration or is synchronously reading from the internal peripherals (SAM = 1), one additional
wait state will be inserted in external master cycle to external memory and peripherals and
also in every cycle from the external master to MC68302 internal memory and peripherals.
When EMWS is cleared, all synchronous internal accesses will be with zero wait states,
and the chip-select logic will generate DTACK after the exact programmed number of wait
states. The chip-select lines are asserted slightly earlier for internal master memory cy-
cles than for an external master. EMWS should be set whenever these timing differences
will necessitate an additional wait state for external masters. After system reset, this bit
defaults to zero.
ADCE—Address Decode Conflict Enable
0 = BERR is not asserted by a conflict in the chip-select logic when two or more chip-
select lines are programmed to overlap the same area.
1 = BERR is asserted by a conflict in the chip-select logic when two or more chip-select
lines are programmed to overlap the same area.
After system reset, this bit defaults to zero.
ADC will be set, regardless of the value of ADCE.
BCLM—Bus Clear Mask
0 = The arbiter does not use the M68000 core internal IPEND signal to assert the in-
ternal and external bus clear signals.
1 = The arbiter uses the M68000 core internal IPEND signal to assert the internal and
external bus clear signals.
MOTOROLA
NOTE
NOTE
MC68302 USER'S MANUAL
System Integration Block (SIB)
3-53
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