Transparent Mask Register (Sccm; E.3.1.2.5 Transparent Mask Register (Sccm) - Motorola MC68302 User Manual

Integrated multiprotocol processor
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CTS—Clear-To-Send Status Changed
0 = No interrupt.
1 = A change in the status of CTS was detected.
CD—Carrier Detect Status Changed
0 = No interrupt.
1 = A change in the status of CD was detected.
TXE—Tx Error
0 = No interrupt.
1 = An error (CTS lost or underrun) occurred on the transmitter channel.
RCH—Receive Character
0 = No interrupt.
1 = A 16-bit word was received on the transparent channel.
BSY—Busy Condition
0 = No interrupt.
1 = A frame was received and discarded due to lack of buffers.
TX—Tx Buffer
0 = No interrupt.
1 = A buffer has been transmitted on the transparent channel (set only if the I bit in the
Tx buffer descriptor is set).
RX—Rx Buffer
0 = No interrupt.
1 = A buffer was received on the transparent channel (set only if the I bit in the Rx buff-
er descriptor is set).
E.3.1.2.5 Transparent Mask Register (SCCM). This 8-bit register is located at offset $88A
(SCC1), $89A (SCC2), and $8AA (SCC3) on D15-D8 of a 16-bit data bus. The SCCM is
used to enable and disable interrupt events reported by the SCCE. The mask bits corre-
spond to the interrupt event bit shown in the SCCE. A bit should be set to a one to enable
the corresponding interrupt in the SCCE. Note that reserved bits in registers should be writ-
ten as zeros.
MOTOROLA
7
6
5
4
CTS
CD
TXE
7
6
5
4
CTS
CD
TXE
MC68360 USER'S MANUAL
SCC Programming Reference
3
2
1
0
RCH
IBSY
TX
RX
3
2
1
0
RTE
IBSY
TX
RX
E-37

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