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Communications Processor (CP)
If the L bit is set, the frame ends, and the transmission of ones resumes until a new buffer
is made ready. RTS is negated during this period. Regardless of whether or not the next
buffer is available immediately, the next buffer will not begin transmission until achieving
synchronization.
The transmit buffer length and starting address may be even or odd; however, since the
transparent transmitter reads a word at a time, better performance can be achieved with an
even buffer length and starting address. For example, if a transmit buffer begins on an odd-
byte boundary and is 10 bytes in length (the worst case), six word reads will result, even
though only 10 bytes will be transmitted.
Any whole number of bytes may be transmitted. If the REVD bit in the transparent mode reg-
ister is set, each data byte will be reversed in its bit order before transmission.
If the interrupt (I) bit in the Tx BD is set, then the TX bit will be set in the transparent event
register following the transmission of the buffer. The TX bit can generate a maskable inter-
rupt.
4.5.16.2 Transparent Channel Buffer Reception Processing
When the M68000 core enables the transparent receiver, it will enter hunt mode. In this
mode, it waits to achieve synchronization before receiving data. See 4.5.16.5 Transparent
Synchronization for details.
Once data reception begins, the transparent receiver begins moving data from the receive
FIFO to the receive buffer, always moving a 16-bit word at a time. After each word is moved
to memory, the RCH bit in the transparent event register is set, which can generate a
maskable interrupt, if desired. The transparent receiver continues to move data to the re-
ceive buffer until the buffer is completely full, as defined by the byte count in MRBLR. The
receive buffer length (stored in MRBLR) and starting address must always be even, so the
minimum receive buffer length must be 2.
After a buffer is filled, the transparent receiver moves to the next Rx BD in the table and be-
gins moving data to its associated buffer. If the next buffer is not available when needed, a
busy condition is signified by the setting of the BSY bit in the transparent event register,
which can generate a maskable interrupt.
Received data is always packed into memory a word at a time, regardless of how it is re-
ceived. For example, in NMSI mode, the first word of data will not be moved to the receive
buffer until after the sixteenth receive clock occurs. In PCM highway mode, the same prin-
ciple applies except that the clocks are only internally active during an SCC time slot. For
example, if each SCC time slot is seven bits long, the first word of data will not be moved to
the receive buffer until after the second bit of the third time slot, regardless of how much time
exists between individual time slots.
Once synchronization is achieved for the receiver, the reception process continues unabat-
ed until a busy condition occurs, a CD lost condition occurs, or a receive overrun occurs.
The busy condition error should be followed by an ENTER HUNT MODE command to the
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MC68302 USER'S MANUAL
MOTOROLA
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