Figure 6-4. Read-Modify-Write Cycle Timing Diagram - Motorola MC68302 User Manual

Integrated multiprotocol processor
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S0
S1
S2
CLKO
AS
(NOTE 2)
(OUTPUT)
9
AS
(NOTE 3)
(OUTPUT)
RMC
(OUTPUT)
UDS–LDS
(OUTPUT)
18
R/W
(OUTPUT)
DTACK
D15–D0
NOTES:
1. For other timings than RMC, see Figures 6-2 and 6-3.
2. RMCST = 0 in the SCR.
3. RMCST = 1 in the SCR.
4. Wait states may be inserted between S4 and S5 during the write cycle and between S16 and S17 during the read cycle.
5. Read-modify-write cycle is generated only by the TAS instruction.

Figure 6-4. Read-Modify-Write Cycle Timing Diagram

MOTOROLA
S3
S4
S5
S6
S7
S8
12
62
27
DATA IN
INDIVISIBLE CYCLE
MC68302 USER'S MANUAL
S9
S10 S11
S12
S13 S14 S15 S16 S17 S18
9
20
23
29
Electrical Characteristics
S19
12
63
9
18
25
DATA OUT
6-11

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