Bisync Error-Handling Procedure - Motorola MC68302 User Manual

Integrated multiprotocol processor
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Communications Processor (CP)
cludes it from the BCS. If the second character is a DLE, the BISYNC controller will write it
to the buffer and include it in the BCS. If the character is not a DLE or SYNC, the BISYNC
controller will examine the control characters table and act accordingly. If the character is
not in the table, the buffer will be closed with the DLE follow character error (DL) bit set. If
the V bit is not set, the receiver will treat the character as a normal character.
When using 7-bit characters with parity, the parity bit should be
included in the DLE register value.
15
14
13
12
V
0
0

4.5.13.8 BISYNC Error-Handling Procedure

The BISYNC controller reports message reception and transmission error conditions using
the channel BDs, the error counters, and the BISYNC event register. The modem interface
lines can also be directly monitored in the SCC status register.
Transmission Errors:
1. Transmitter Underrun. When this error occurs, the channel terminates buffer transmis-
sion, closes the buffer, sets the underrun (UN) bit in the BD, and generates the TXE
interrupt (if enabled). The channel resumes transmission after the reception of the RE-
START TRANSMIT command. Underrun cannot occur between frames or during a
DLE-XXX pair in transparent mode. The FIFO size is three bytes in BISYNC.
2. Clear-To-Send Lost During Message Transmission. When this error occurs and the
channel is not programmed to control this line with software, the channel terminates
buffer transmission, closes the buffer, sets the CTS lost (CT) bit in the BD, and gener-
ates the TXE interrupt (if enabled). The channel will resume transmission after the re-
ception of the RESTART TRANSMIT command.
Reception Errors:
1. Overrun Error. The BISYNC controller maintains an internal three-byte FIFO for re-
ceiving data. The CP begins programming the SDMA channel (if the data buffer is in
external memory) and updating the CRC when the first word is received into the FIFO.
If a FIFO overrun occurs, the BISYNC controller writes the received data byte to the
internal FIFO over the previously received byte. The previous character and its status
bits are lost. Following this, the channel closes the buffer, sets the overrun (OV) bit in
the BD, and generates the RX interrupt (if enabled). The receiver then enters hunt
mode immediately.
2. Carrier Detect Lost During Message Reception. When this error occurs and the chan-
nel is not programmed to control this line with software, the channel terminates mes-
sage reception, closes the buffer, sets the carrier detect lost (CD) bit in the BD, and
generates the RX interrupt (if enabled). This error is the highest priority; the rest of the
message is lost and no other errors are checked in the message. The receiver then
enters hunt mode immediately.
3. Parity Error. When this error occurs, the channel writes the received character to the
4-90
11
10
9
0
0
0
0
MC68302 USER'S MANUAL
NOTE
8
7
6
5
0
4
3
2
1
DLE
MOTOROLA
0

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