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Signal Description
DREQ/PA13—DMA Request
This input is asserted by a peripheral device to request an operand transfer between that
peripheral device and memory. In the cycle steal request generation mode, this input is
edge-sensitive. In burst mode, it is level-sensitive.
DACK/PA14—DMA Acknowledge
This output, asserted by the IDMA, signals to the peripheral that an operand is being trans-
ferred in response to a previous transfer request.
DONE/PA15—DONE
This bidirectional, open-drain signal is asserted by the IDMA or by a peripheral device during
any IDMA bus cycle to indicate that the data being transferred is the last item in a block. The
IDMA asserts this signal as an output during a bus cycle when the byte count register is dec-
remented to zero. Otherwise, this pin is an input to the IDMA to terminate IDMA operation.
5.17 IACK OR PIO PORT B PINS
The IACK or PIO port B pins are shown in Figure 5-14.
Each one of these three pins can be used either as an interrupt acknowledge signal or as a
general-purpose parallel I/O port. Note that the IMP interrupt controller does not require the
use of the IACK pins when it supplies the interrupt vector for the external source. The input
buffers have Schmitt triggers.
IACK7/PB0
IACK6/PB1
IACK1/PB2—Interrupt Acknowledge/Port B I/O
As IACK1, IACK6, and IACK7, these active low output signals indicate to the external device
that the MC68302 is executing an interrupt acknowledge cycle. The external device must
then place its vector number on the lower byte of the data bus or use AVEC for autovectoring
(unless internal vector generation is used).
5.18 TIMER PINS
The timer pins are shown in Figure 5-15.
5-20
MC68302
Figure 5-14. IACK or PIO Port B Pins
MC68302 USER'S MANUAL
IACK7 / PB0
IACK6 / PB1
IACK1 / PB2
MOTOROLA
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