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I—Interrupt
0 = No interrupt is generated after this buffer has been used.
1 = When this buffer has been closed by the transparent controller, the RX bit in the
transparent event register will be set, which can cause an interrupt.
The following status bits are written by the CP after the received data has been placed into
the associated data buffer.
Bits 11–2—Reserved for future use. Should be written with zero by the user.
OV—Overrun
A receiver overrun occurred during reception.
CD—Carrier Detect Lost
The carrier detect signal was negated during buffer reception.
Data Length
The data length is the number of octets that the CP has written into this BD's data buffer.
It is written only once by the CP as the buffer is closed.
The actual buffer size should be greater than or equal to the
MRBLR.
Rx Buffer Pointer
The receive buffer pointer, which always points to the first location of the associated data
buffer, must be even. The buffer may reside in either internal or external memory.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
4.5.16.9 Transparent Transmit Buffer Descriptor (Tx BD)
Data is presented to the CP for transmission on an SCC channel by arranging it in buffers
referenced by the channel's Tx BD table. The CP confirms transmission (or indicates error
conditions) using the BDs to inform the processor that the buffers have been serviced. The
Tx BD is shown in Figure 4-43.
15
14
OFFSET + 0
R
X
OFFSET + 2
OFFSET + 4
OFFSET +6
Figure 4-43. Transparent Transmit Buffer Descriptor
The first word of the Tx BD contains status and control bits. These bits are prepared by the
user before transmission and are set by the CP after the buffer has been transmitted.
MOTOROLA
13
12
11
10
W
I
L
—
TX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
MC68302 USER'S MANUAL
Communications Processor (CP)
NOTE
NOTE
9
8
7
6
—
—
—
—
DATA LENGTH
5
4
3
2
—
—
—
—
1
0
UN
CT
4-131
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