Figure 3-9. Chip-Select Block Diagram - Motorola MC68302 User Manual

System Integration Block (SIB)
R/W
The user should not normally program more than one chip-select line to the same area.
When this occurs, the address compare logic will set address decode conflict (ADC) in the
system control register (SCR) and generate BERR if address decode conflict enable
(ADCE) is set. Only one chip-select line will be driven because of internal line priorities. CS0
has the highest priority, and CS3 the lowest. BERR will not be asserted on write accesses
to the chip-select registers.
If one chip select is programmed to be read-only and another chip select is programmed to
be write-only, then there will be no overlap conflict between these two chip selects, and the
ADC bit will not be set.
When a bus master attempts to write to a read-only location, the chip-select logic will set
write protect violation (WPV) in the SCR and generate BERR if write protect violation enable
(WPVE) is set. The CS line will not be asserted.
The chip-select logic is reset only on total system reset (asser-
tion of RESET and HALT). Accesses to the internal RAM and
registers, including the system configuration registers (BAR and
3-44
BASE REGISTER 0 (BR0)
COMPARE LOGIC
OPTION REGISTER 0 (OR0)
CS0
CS1
CS2
CS3
DTACK GENERATION

Figure 3-9. Chip-Select Block Diagram

NOTE
MC68302 USER'S MANUAL
CS0
CS1
CS2
CS3
DTACK
MOTOROLA