Mdio Interface - Xilinx LogiCORE IP MAC v8.5 User Manual

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MDIO Interface

Table 2-9
76.
Table 2-9: MDIO Interface Signal Pinout
mdc
mdio_in
mdio_out
mdio_tri
1. mdio_in, mdio_out
30
-- DISCONTINUED PRODUCT --
describes the MDIO Interface signals. See
Signal Direction
Output
1
Input
1
Output
1
Output
and
mdio_tri
signal suitable for connection to an external PHY.
www.xilinx.com
"Using the MDIO interface," on page
Clock
Domain
host_clk Management Clock: programmable
frequency derived from host_clk.
host_clk Input data signal for communication with
PHY configuration and status. Tie high if
unused.
host_clk Output data signal for communication
with PHY configuration and status.
host_clk Tristate control for MDIO signals; 0 signals
that the value on mdio_out should be
asserted onto the MDIO bus.
can be connected to a Tri-state buffer to create a bi-directional
1-Gigabit Ethernet MAC v8.5 User Guide
Chapter 2: Core Architecture
Description
UG144 April 24, 2009
mdio