Receive Fifo - Xilinx LogiCORE IP MAC v8.5 User Manual

Interfaces

Receive FIFO

Table A-3
client interface, see
Table A-3: Receive FIFO Client Interface
rx_clk
rx_reset
rx_enable
rx_data[7:0]
rx_data_valid
rx_good_frame
rx_bad_frame
rx_overflow
Table A-4
LocalLink interface, see
Table A-4: Receive FIFO LocalLink Interface
rx_ll_clock
rx_ll_reset
rx_ll_data_out[7:0]
rx_ll_sof_out_n
rx_ll_eof_out_n
rx_ll_src_rdy_out_n
rx_ll_dst_rdy_in_n
rx_fifo_status[3:0]
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
describes the receive FIFO client interface. For more information on the MAC
"Receiving Inbound Frames," on page
Signal Direction
Input
Input
Input
Input
Input
Input
Input
Output
describes the receive FIFO LocalLink interface. For more information on the
"Overview of LocalLink Interface," on page
Signal Direction
Input
Input
Output
Output
Output
Output
Input
Output
www.xilinx.com
39.
Clock
Description
Domain
N/A Receive clock used by MAC
rx_clk Synchronous reset
rx_clk Clock enable for rx_clk, tie to logic 1
when using GEMAC
rx_clk Data received from MAC
rx_clk Valid signal for data
rx_clk Indicates if frame is valid and should
be accepted by client
rx_clk Indicates if frame is invalid and
should be dropped by the FIFO
rx_clk Overflow signal indicates when a
frame has been dropped in the FIFO
Clock
Description
Domain
N/A Read clock for LocalLink interface
rx_ll_clock Synchronous reset
rx_ll_clock Data read from FIFO
rx_ll_clock Start of frame indicator
rx_ll_clock End of frame indicator
rx_ll_clock Source ready indicator
rx_ll_clock Destination ready indicator
rx_ll_clock FIFO memory status
R
130.
129