Mdio Interface; Figure 8-4: Address Table Read Timing - Xilinx LogiCORE IP MAC v8.5 User Manual

-- DISCONTINUED PRODUCT --
R
Chapter 8: Configuration and Status
hostclk
hostmiimsel
hostopcode[1]
0x18C
hostaddr[8:0]
hostaddr[9]
hostwrdata[23]
LOCATION
hostwrdata[17:16]
31 : 0 47 : 32
hostrddata[31:0]

Figure 8-4: Address Table Read Timing

MDIO Interface

Introduction to MDIO
The MDIO interface for 1 Gbps operation (and slower speeds) is defined in IEEE 802.3
clause 22. This is a two wire interface consisting of a clock, mdc, and a shared serial data
line, mdio.
An MDIO bus in a system consists of a single Station Management (STA) master
management entity and a number of MDIO Managed Device (MMD) slave entities.
Figure 8-5 illustrates a typical system. All transactions are initiated by the STA entity. The
GEMAC core implements a STA and can be connected to MMDs (PHY devices) to access
their management registers.
86 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009