Preface: About This Guide; Guide Contents - Xilinx LogiCORE IP MAC v8.5 User Manual

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About This Guide
The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about
generating the core, customizing and simulating the core utilizing the provided example
design, and running the design files through implementation using the Xilinx tools.

Guide Contents

This guide contains the following chapters:
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1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
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Preface, "About this Guide"
and the conventions used in this document.
Chapter 1, "Introduction"
recommended design experience, additional resources, technical support, and
submitting feedback to Xilinx.
Chapter 2, "Core Architecture"
Physical/Client signal interfaces.
Chapter 3, "Generating the Core"
to generate the core.
Chapter 4, "Designing with the Core"
describe design parameters, including how to initialize the core, generate and
consume core packets, and how to operate the Management Interface.
Chapter 9, "Constraining the Core"
Chapter 10, "Clocking and Resetting"
associated with clock management logic, including the Gigabit Media Independent
Interface (GMII) and Reduced Gigabit Media Independent Interface (RGMII) options.
Chapter 11, "Interfacing to Other Cores"
Ethernet MAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core and the
Ethernet Statistics core.
Chapter 12, "Implementing Your Design"
synthesis, simulation, and implementation environments and how to generate a
bitstream through the design flow.
Appendix A, "Using the Client-Side FIFO"
example design that accompanies the GEMAC core.
Appendix B, "Core Verification, Compliance, and Interoperability"
core was verified and certified for compliance.
Appendix C, "Calculating DCM Phase-Shifting"
calculate the system timing requirements when using DCMs with the core.
Appendix D, "Core Latency"
www.xilinx.com
introduces the organization and purpose of the guide
describes the core and related information, including
provides an overview of the core and discusses the
describes the graphical user interface options used
through Chapter 8, "Configuration and Status"
describes the constraints associated with the core.
discusses special design considerations
describes how to interface the 1-Gigabit
provides instructions for how to set up
describes the FIFO provided in the
provides information about how to
describes the latency of the core.
Preface
describes how the
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