Chapter 9: Constraining The Core - Xilinx LogiCORE IP MAC v8.5 User Manual

R
PERIOD Constraints for Clock Nets
gtx_clk
The clock provided to gtx_clk must be constrained for a clock frequency of 125 MHz.
The following UCF syntax shows the necessary constraints being applied to the
gtx_clk
gmii_rx_clk (for GMII Example Designs)
The clock provided to
The following UCF syntax shows the necessary constraints being applied to the clock
(which is routed to the
rgmii_rxc (for RGMII Example Designs)
The receiver clock provided by the RGMII must be constrained for a clock frequency of 125
MHz.
The following UCF syntax shows the necessary constraints being applied to the clock
(which is routed to the
host_clk
The clock provided to
allowable range (see
The following UCF syntax shows a 100 MHz period constraint being applied to the
host_clk
MDIO Logic
The MDIO logic (see
data only changes at the mdc output rate (as configured in the
page
MDIO logic is clocked with host_clk, but is sent a clock enable pulse at the mdc
frequency. To prevent this logic being over constrained by the host_clk period, the
relevant flip-flops for the MDIO logic can be grouped together and removed from the
host_clk period constraint. This is shown in the previous UCF syntax for host_clk
94
-- DISCONTINUED PRODUCT --
(which is routed to the gtx_clk port of the core):
_bufg signal
# Set the Transmitter clock period constraints: please do not relax
NET "gtx_clk_bufg"
TIMEGRP "tx_clock"
TIMESPEC "TS_tx_clk"
gmii_rx_clk
gmii_rx_clk
# Set the Receiver clock period constraints: please do not relax
NET "gmii_rx_clk" TNM_NET = "gmii_rx_clk";
TIMESPEC "TS_gmii_rx_clk" = PERIOD "gmii_rx_clk" 8000 ps HIGH 50 %;
TIMEGRP "rx_clock"
gmii_rx_clk
# Set the Receiver clock period constraints: please do not relax
NET "gmii_rx_clk_bufg"
TIMEGRP "rx_clock"
TIMESPEC "TS_rx_clk"
host_clk
"Host Clock Frequency," on page
(which is routed to the host_clk port of the core):
signal
# Set the Management Clock period constraints: relax as required
NET "host_clk" TNM_NET
TIMEGRP "host"
TIMESPEC "TS_host_clk"
"MDIO Interface," on page
82). Nominally mdc will be set to a frequency of 2.5 MHz. Every flip-flop in the
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Chapter 9: Constraining the Core

TNM_NET = "clk_tx";
= "clk_tx";
= PERIOD "tx_clock" 8000 ps HIGH 50 %;
must be constrained for a clock frequency of 125 MHz.
port of the core)
= "gmii_rx_clk";
port of the core):
TNM_NET = "clk_rx";
= "clk_rx";
= PERIOD "rx_clock" 8000 ps HIGH 50 %;
must be constrained to the desired frequency within the
77).
= "host_clk";
= "host_clk" EXCEPT "mdio_logic";
= PERIOD "host" 10000 ps HIGH 50 %;
30) is synchronous to host_clk
1-Gigabit Ethernet MAC v8.5 User Guide
signal
signal
but
,
"MDIO Configuration," on
.
UG144 April 24, 2009