Xilinx LogiCORE IP MAC v8.5 User Manual page 92

R
Table 8-13: Configuration Vector Bit Definition (Continued)
Bit(s)
62
63
64
66:65
67
92
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Configuration
Register cross Clock
reference
"Flow Control gtx_clk
Configuration
Word" bit 30
"Receiver gtx_clk
Configuration
Word 1" bit 25
"Address Filter gmii_rx_clk
Mode" bit 31
n/a n/a
"Receiver gtx_clk
Configuration
Word 1" bit 24
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Chapter 8: Configuration and Status
Description
Receive Flow Control Enable. When this bit
is '1,' received flow control frames will inhibit
the transmitter operation. When at '0,'
received flow frames are passed up to the
client.
Length/Type Error Check Disable. When
this bit is set to '1,' the core will not perform
the length/type field error checks as
described in "Length/Type Field Error
Checks," on page 43. When this bit is set to
'0,' the length/type field checks will be
performed: this is normal operation.
Address Filter Enable. When this bit is '0,'
the Address Filter is enabled. If it is set to '1,'
the Address Filter will operate in
promiscuous mode.
This input is unused.
Control Frame Length Check Disable When
this bit is set to '1,' the core will not mark
control frames as 'bad' if they are greater than
the minimum frame length.
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009