Figure 7-6: External Rgmii Transmitter Logic In Virtex-5 Devices - Xilinx LogiCORE IP MAC v8.5 User Manual

Implementing External RGMII
Virtex-5 Devices
The same logic that is used in
devices. However, an alternative solution has been adopted for the example design
delivered with the core.
core to create an external RGMII in a Virtex-5 device. The signal names and logic shown
exactly match those delivered with the example design when the RGMII is selected.
Figure 7-6
ODDR components. These components convert the input signals into one double-data-rate
signal. The ODDR outputs are passed through IODELAYs—and these can be used to
adjust the relationship between the individual signals. These signals are then output
through OBUFs before being driven to output pads.
IOB LOGIC
IBUFG
gtx_clk
IPAD
1-Gigabit Ethernet MAC Core
gtx_clk

Figure 7-6: External RGMII Transmitter Logic in Virtex-5 Devices

1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
Figure 7-5
Figure 7-6 shows using the physical transmitter interface of the
also shows that the output transmitter signals are registered in the IOBs in
gtx_clk_bufg
gmii_txd_int[0]
gmii_txd[0]
gmii_txd_int[4]
gmii_txd[4]
gmii_tx_en_int
gmii_tx_en
gmii_tx_er_int
gmii_tx_er
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can also be used without modification for Virtex-5
IOB LOGIC
ODDR
'1'
D1
'0' D2
Q IODELAY
C
IOB LOGIC
ODDR
D1
D2
Q
IODELAY
C
IOB LOGIC
ODDR
D1
D2
Q IODELAY
C
R
OBUF
rgmii_txc
OPAD
OBUF
rgmii_txd[0]
OPAD
OBUF
rgmii_tx_ctl
OPAD
69