Figure 7-5: External Rgmii Transmitter Logic In Virtex-4 Devices - Xilinx LogiCORE IP MAC v8.5 User Manual

R
IOB LOGIC
IBUFG
gtx_clk
IPAD
1-Gigabit Ethernet MAC Core
gtx_clk

Figure 7-5: External RGMII Transmitter Logic in Virtex-4 Devices

The logic required to forward the transmitter clock is also shown: this uses an ODDR
register so that the clock signal produced incurs exactly on the same delay as the data and
control signals. The rgmii_tx_clk clock signal is phase-shifted by 90 degrees in the
DCM with respect to gtx_clk_bufg. This means that the rising edge of rgmii_txc
occurs in the center of the data valid window—which maximizes setup and hold times
across the interface, as specified in the RGMII v2.0 specification.
The use of the BUFGMUX shown, with one input connected to the DCM CLK90 output is
included so that a reliable 125MHz clock source is always provided on global routing
(when the DCM is held in reset, the DCM input clock is instead selected). This is required
to always provided a reliable clock for the receiver logic DCM: see
68
-- DISCONTINUED PRODUCT --
BUFGMUX
DCM
rgmii_tx_clk_bufg
CLK90
CLKIN
gtx_clk_bufg
CLK0
FB
gmii_txd_int[0]
gmii_txd[0]
gmii_txd_int[4]
gmii_txd[4]
gmii_tx_en_int
gmii_tx_en
gmii_tx_er_int
gmii_tx_er
www.xilinx.com
Chapter 7: Using the Physical Side Interface
IOB LOGIC
ODDR
'1' D1
'0' D2
Q
C
IOB LOGIC
ODDR
D1
D2
Q
C
IOB LOGIC
ODDR
D1
D2
Q
C
1-Gigabit Ethernet MAC v8.5 User Guide
OBUF
rgmii_txc
OPAD
OBUF
rgmii_txd[0]
OPAD
OBUF
rgmii_tx_ctl
OPAD
"DCM Reset circuitry".
UG144 April 24, 2009