Reset Conditions; Figure 10-4: Clock Management Logic With External Rgmii (Multiple Cores); Figure 10-5: Reset Circuit For A Single Clock/Reset Domain - Xilinx LogiCORE IP MAC v8.5 User Manual

R
gtx_clk

Reset Conditions

Internally, the core is divided up into clock/reset domains that group together elements
with common clock and reset signals. The reset circuitry for one of these domains is
illustrated in
the design.
112
-- DISCONTINUED PRODUCT --
BUFG
DCM
CLK_0
IBUFG
BUFG
CLK_90
RGMII Tx Logic
RGMII Tx Logic

Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores)

Figure 10-5. This circuit provides controllable skews on the reset nets within
reset
Configuration reset
'0'
Clock

Figure 10-5: Reset Circuit for a Single Clock/reset Domain

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Chapter 10: Clocking and Resetting
1-Gigabit Ethernet MAC Core
gtx_clk gmii_rx_clk
RGMII Rx Logic
1-Gigabit Ethernet MAC Core
gtx_clk gmii_rx_clk
RGMII Rx Logic
PRE PRE PRE PRE
D Q D Q D Q D Q
C C C C
FDP FDP FDP FDP
1-Gigabit Ethernet MAC v8.5 User Guide
BUFG
DCM
CLK_0
IBUFG
rgmii_rxc1
BUFG
DCM
CLK_0
IBUFG
rgmii_rxc2
Core Registers
PRE PRE PRE
UG144 April 24, 2009