Figure 7-9: External Rgmii Receiver Logic For Virtex-5 Devices - Xilinx LogiCORE IP MAC v8.5 User Manual

R
Virtex-5 Devices
Figure 7-9
RGMII in a Virtex-5 device. The signal names and logic exactly match those delivered with
the example design when RGMII is selected.
Figure 7-9
components. These components convert the input double data rate signals into GMII
specification signals. The gmii_rx_er_int signal is derived in the FPGA fabric from the
outputs of the control IDDR component.
1-Gigabit Ethernet MAC Core

Figure 7-9: External RGMII Receiver Logic for Virtex-5 Devices

The IODELAY components are used to phase-shift the input RGMII clock, data and control
signals to meet the setup and hold margins. The IODELAY components are used in fixed
delay mode, where the attribute IDELAY_VALUE determines the tap delay value. An
IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5
User Guide for more information on the use of IDELAYCTRL and IODELAY components.
74
-- DISCONTINUED PRODUCT --
shows using the physical receiver interface of the core to create an external
also shows that the input receiver signals are registered in the IOBs in IDDR
BUFG
gmii_rx_clk_bufg
gmii_rx_clk
gmii_rxd_int[0]
gmii_rxd[0]
gmii_rxd_int[4]
gmii_rxd[4]
gmii_rx_dv_int
gmii_rx_dv
gmii_rx_er_int
gmii_rx_er
www.xilinx.com
Chapter 7: Using the Physical Side Interface
IOB LOGIC
IODELAY
IOB LOGIC
IDDR
Q1
IODELAY
Q2
D
C
IOB LOGIC
IDDR
Q1
IODELAY
D
Q2
C
1-Gigabit Ethernet MAC v8.5 User Guide
IBUFG
rgmii_rxc
IPAD
IBUF
rgmii_rxd[0]
IPAD
IBUF
rgmii_rx_ctl
IPAD
UG144 April 24, 2009