Figure 7-8: External Rgmii Receiver Logic For Virtex-4 Devices - Xilinx LogiCORE IP MAC v8.5 User Manual

Implementing External RGMII
•
1-Gigabit Ethernet MAC Core

Figure 7-8: External RGMII Receiver Logic for Virtex-4 Devices

1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
This can be achieved by connecting the reset_200ms signal to the
reset_200ms_in signal at any level of example design HDL hierarchy.
gmii_rx_clk_bufg
gmii_rx_clk
gmii_rxd_int[0]
gmii_rxd[0]
gmii_rxd_int[4]
gmii_rxd[4]
gmii_rx_dv_int
gmii_rx_dv
gmii_rx_er_int
gmii_rx_er
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BUFG
DCM
CLKIN
CLK0
IDDR
Q1
Q2
D
C
IDDR
Q1
D
Q2
C
IOB LOGIC
IBUFG
rgmii_rxc
IPAD
FB
IOB LOGIC
IBUF
rgmii_rxd[0]
IPAD
IOB LOGIC
IBUF
rgmii_rx_ctl
IPAD
R
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