Figure 8-1: Configuration Register Write Timing; Figure 8-2: Configuration Register Read Timing - Xilinx LogiCORE IP MAC v8.5 User Manual

R
Reading from the configuration register words is similar, but the upper host_opcode bit
should be '1,' as shown in
host_rd_data the host_clk edge after the register address is asserted onto
host_addr.
84
-- DISCONTINUED PRODUCT --
host_clk
host_miim_sel
host_opcode[1]
host_addr[8:0]
host_addr[9]
host_wr_data[31:0]

Figure 8-1: Configuration Register Write Timing

Figure 8-2. In this case, the contents of the register appear on
host_clk
host_miim_sel
host_opcode[1]
host_addr[8:0]
host_addr[9]
host_rd_data[31:0]

Figure 8-2: Configuration Register Read Timing

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Chapter 8: Configuration and Status
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009