Figure 7-3: External Gmii Receiver Logic For Virtex-5 Devices - Xilinx LogiCORE IP MAC v8.5 User Manual

Implementing External GMII
Virtex-5 Devices
An IODELAY component may be used on the clock, data and control paths, as illustrated
in
and control signals to meet the setup and hold requirements of GMII and to allow for any
bus skew across the data and control inputs. The IODELAY components are used in fixed
delay mode, where the attribute IDELAY_VALUE determines the tap delay value. An
IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5
FPGA User Guide for more information on the use of IDELAYCTRL and IODELAY
components.
1-Gigabit Ethernet MAC LogiCORE

Figure 7-3: External GMII Receiver Logic for Virtex-5 Devices

1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
Figure 7-3. These can be used to either shift the input clock gmii_rx_clk or the data
gmii_rx_clk
gmii_rxd_reg[0]
gmii_rxd[0]
gmii_rx_dv_reg
gmii_rx_dv
gmii_rx_er_reg
gmii_rx_er
www.xilinx.com
BUFG
IODELAY
IODELAY
Q D
IODELAY
Q D
IODELAY
Q D
IOB LOGIC
IBUFG
gmii_rx_clk
IPAD
IBUF
gmii_rxd[0]
IPAD
IBUF
gmii_rx_dv
IPAD
IBUF
gmii_rx_er
IPAD
R
65