Chapter 8: Configuration And Status - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
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R
Table 8-4: Receiver Configuration Word 1 (Continued)
29
30
31
Transmitter Configuration
The register contents for the Transmitter Configuration Word are described in
Table 8-5: Transmitter Configuration Word
Bit
24-0
25
26
27
28
80
-- DISCONTINUED PRODUCT --
Default
Bit
Value
0
In-band FCS Enable When this bit is '1,' the MAC receiver
will pass the FCS field up to the client. When at '0,' the
client will not be passed the FCS. In both cases, the FCS
will be verified on the frame.
0
Jumbo Frame Enable When this bit is set to '1,' the MAC
receiver will accept frames over the specified IEEE 802.3-
2005 maximum legal length. When this bit is '0,' the MAC
will only accept frames up to the specified maximum.
0
Reset When this bit is set to '1,' the receiver will be reset.
The bit will then automatically revert to '0.' This reset also
sets all of the receiver configuration registers to their
default values.
Default
Description
Value
n/a
Reserved
0
Interframe Gap Adjust Enable If '1,' the transmitter will
read the value on the port tx_ifg_delay at the start of frame
transmission and adjust the interframe gap following the
frame accordingly.
n/a
Reserved
0
VLAN Enable When this bit is set to '1,' the transmitter
will allow the transmission of VLAN tagged frames.
1
Transmit Enable When this bit is '1,' the transmitter is
operational. When it is '0,' the transmitter is disabled.
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Chapter 8: Configuration and Status

Description
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Table
8-5.

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