Physical Side Interface - Xilinx LogiCORE IP MAC v8.5 User Manual

Core Interfaces
Configuration Vector (Optional)
Table 2-6
Configuration Vector uses direct inputs to the core to replace the functionality of the MAC
configuration bits. See
Table 2-6: Optional Configuration Vector Signal Pinout
configuration_vector[67:0]
Note: All bits are registered on input but may be treated as asynchronous inputs.
Asynchronous Reset
Table 2-7
Table 2-7: Reset Signal
reset

Physical Side Interface

GMII
Table 2-8
Physical Side Interface."
Table 2-8: GMII Interface Signal Pinout
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rx_clk
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
describes the alternative to the optional Management Interface signals. The
"Access without the Management Interface," on page
Signal
describes the asynchronous reset signal for the entire core.
Signal Direction
Input
describes the GMII-style interface signals of the core. See
Signal Direction
Output
Output
Output
Input
Input
Input
Input
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Direction
Input Used to replace the functionality of
the MAC Configuration Registers
when the Management Interface is
not used
Clock Domain
n/a Asynchronous reset for entire core
Clock Domain
gtx_clk Transmit data from MAC
gtx_clk Transmit control signal from MAC
gtx_clk Transmit control signal from MAC
n/a Receive clock from external PHY (125
MHz)
gmii_rx_clk Received data to MAC
gmii_rx_clk Received control signal to MAC
gmii_rx_clk Received control signal to MAC
90.
Description
Description
Chapter 7, "Using the
Description
29
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