Xilinx LogiCORE IP MAC v8.5 User Manual page 121

Ug144 1-gigabit ethernet
Table of Contents

Advertisement

Ethernet Statistics Core
The management interfaces of the two cores can be shared by avoiding bus conflict, as
follows:
Table 11-1
(as illustrated in
Table 11-1: Management Interface Transaction Types
Configuration
MIIM access
Statistics Read
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
Selecting a different address range for the statistics to that of the MAC configuration
registers. This is achieved by setting host_addr[9] to logic 0 when reading from the
statistics and logic 1 when writing and reading to the MAC configuration registers.
Using the host_miim_sel signal to differentiate between a statistical counter read
and a MAC initiated MDIO transaction. This is achieved by setting host_miim_sel
to logic 0 for a statistical counter read and logic 1 for a MAC initiated MDIO
transaction.
describes the type of host transactions that occur if the host interface is shared
Figure
11-5).
Transaction
www.xilinx.com
host_miim_sel
0
1
0
R
host_addr[9]
1
X
0
121

Advertisement

Table of Contents
loading

Table of Contents