Figure 8-3: Address Table Write Timing - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
Table of Contents

Advertisement

Using the Optional Management Interface
Accessing the Address Table
To write to a specific entry in the address table, you must first write the least significant 32-
bits of the address into the Address Table Configuration (Word 0) register. You then write
the most significant 16 bits together with the location in the table (bits 17–16) to the
Address Table Configuration (Word1) register with bit 23 (read not write) set to '0.' This is
shown in
writes to be on adjacent cycles.
As shown in
1) with the location set to the desired table entry and bit 23 set to '1' to read from the
address table. On the next cycle the least significant word appears on the hostrddata
bus. One cycle afterwards, the most significant 16-bits are output on the lower 16 bits of the
bus.
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
Figure
8-3. Although it is shown in the figure, there is no requirement for the two
hostclk
hostmiimsel
hostopcode[1]
hostaddr[8:0]
hostaddr[9]
hostwrdata[31:0]
BIT31

Figure 8-3: Address Table Write Timing

Figure
8-4, you must write to the Address Table Configuration register (Word
www.xilinx.com
0x188
0x18C
ADDR[31:0]
BIT0
BITS15..0 = ADDR[47:32]
BITS17..16 = LOCATION
BIT23 = 0
R
85

Advertisement

Table of Contents
loading

Table of Contents