Using A Rocketio Transceiver - Xilinx LogiCORE IP MAC v8.5 User Manual

Ethernet 1000Base-X PCS/PMA or SGMII Core
Virtex-5 LXT and SXT Devices
Figure 11-3
the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in
1000BASE-X mode with PMA using the device-specific RocketIO transceiver).
1-Gigabit Ethernet
MAC
LogiCORE
gmii_rx_clk
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
Figure 11-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA
Figure 11-3
•
•
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
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illustrates the connections and clock management logic required to interface
component_name_block
userclk2
(Block Level from example design)
(125 MHz)
Ethernet 1000BASE-X
PCS/PMA or SGMII
gtx_clk
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
mdc
mdc
mdio_in
mdio_in
mdio_out
mdio_out
no
mdio_tri mdio_tri
connection

using a RocketIO transceiver

illustrates the following:
Direct internal connections are made between the GMII interfaces between the two
cores.
If the GEMAC has been generated with the optional Management Interface, the
MDIO port can be connected to that of the Ethernet 1000BASE-X PCS/PMA or SGMII
core to access its embedded configuration and status registers. See
Optional Management Interface."
www.xilinx.com
BUFG
LogiCORE
userclk
userclk2
RocketIO I/F
brefclkp IBUFGDS
IPAD
IPAD
clkin
brefclkn
(125MHz)
Virtex-5
GTP
RocketIO
TXOUTCLK0
CLKIN
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
"Using the
R
117