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R
MDIO Configuration
The register contents for the Management Configuration Word are described in
Table 8-7: Management Configuration Word
4-0
5
31-6
Address Filter Configuration
Table 8-8
configuration when the GEMAC core implemented with an Address Filter. The register
contents for the two unicast address registers are found in
Table 8-8: Unicast Address Word 0
31-0
Table 8-9: Unicast Address Word 1
15-0
31-16
82
-- DISCONTINUED PRODUCT --
Default
Bits
Value
All 0s
Clock Divide[4:0] This value enters a logical equation
which enables the mdc frequency to be set as a divided
down ratio of the host_clk frequency.
0
MDIO Enable When this bit is '1,' the MDIO interface can
be used to access attached PHY devices. When this bit is
'0,' the MDIO interface is disabled and the MDIO signals
remain inactive.
n/a
Reserved
through
Table 8-12
describe the registers used to access the Address Filter
Default
Bits
Value
All 0s
Address filter unicast address[31:0].
The address is ordered so the first byte received is the
lowest positioned byte in the register; for example, a MAC
address of AA-BB-CC-DD-EE-FF would be stored in
Address[47:0] as 0xFFEEDDCCBBAA.
Default
Bits
Value
All 0s
Address filter unicast address[47:32].
N/A
Reserved
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Chapter 8: Configuration and Status
Description
Table 8-8
and
Table
Description
Description
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Table
8-7.
8-9.
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