Appendix D: Core Latency; Transmit Path Latency; Receive Path Latency - Xilinx LogiCORE IP MAC v8.5 User Manual

R
Core Latency

Transmit Path Latency

As measured from a data octet accepted on tx_data[7:0] of the transmitter client-side
interface, until that data octet appears on gmii_txd[7:0] of the physical side GMII style
interface, the latency through the core in the transmit direction is 9 clock periods of
gtx_clk.

Receive Path Latency

As measured from a data octet accepted on gmii_rxd[7:0] of the physical side GMII
style interface, until that data octet appears on rx_data[7:0] of the receiver client-side
interface, the latency through the core in the receive direction is 9 clock periods of
gmii_rx_clk.
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
www.xilinx.com
Appendix D
137