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R
Read Transaction
Figure 8-7
(PHYAD) device returns the 16-bit word from the register at REGAD.
mdc
mdio
Z
Z
1 1 1 0
IDLE
32 bits
PRE
For details of the register map of MMD (PHY layer devices) and a detailed description of
the operation of the MDIO Interface itself, see IEEE 802.3-2005.
Accessing MDIO With GEMAC
More information about MDIO with GEMAC can be found in the following sections of this
guide:
•
•
•
The management interface is also used to access the MDIO interface of the GEMAC core.
The MDIO interface supplies a clock to the connected PHY, mdc. This clock is derived from
the host_clk signal using the value in the Clock Divide[4:0] configuration register.
The frequency of mdc is given by the following equation:
The frequency of mdc given by this equation should not exceed 2.5 MHz to comply with
the IEEE 802.3-2005 specification for this interface. To prevent mdc from being out of
specification, the Clock Divide[4:0] value powers up at 00000. While this value is in
the register, it is impossible to enable the MDIO interface.
For details of the register map of PHY layer devices and a detailed description of the
operation of the MDIO interface itself, see IEEE 802.3-2005.
88
-- DISCONTINUED PRODUCT --
shows a Read transaction; this is defined by OP="10". The addressed MMD
STA drives MDIO
1
1 0 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 Z 0 D15
ST
OP
PRTAD
REGAD
Figure 8-7: MDIO Read Transaction
For the GEMAC port definition of the MDIO, see
"Connecting the MDIO to an Internally Integrated PHY," on page 76
"Connecting the MDIO to an External PHY," on page 76
f
MDC
www.xilinx.com
Chapter 8: Configuration and Status
MMD drives MDIO
D13
D11
D14
D12
D10
TA
16-bit READ DATA
"MDIO Interface" in Chapter 2
f
HOST_CLK
=
------------------------------------------------------------------- -
(
1
+
Clock Divide[4:0]
1-Gigabit Ethernet MAC v8.5 User Guide
D9
D7
D5
D3
D1
D8
D6
D4
D2
D0
)
×
2
UG144 April 24, 2009
Z
Z
IDLE
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