Using The Rocketio Transceiver - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet

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Virtex-5 FXT Devices

Figure 11-4

the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in

1000BASE-X mode with PMA using the device-specific RocketIO transceiver).

CLKIN

1-Gigabit Ethernet

MAC

LogiCORE

Figure 11-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

118

-- DISCONTINUED PRODUCT --

Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA

or SGMII core, the entire GMII is synchronous to a single clock domain. For this

reason, userclk2 is used as the 125 MHz reference clock for both cores and the

transmitter and receiver logic of the GEMAC core now operate in the same clock

domain. This allows clock crossing constraints between the gtx_clk and

gmii_rx_clk clock domains to be removed from the GEMAC UCF. See

for Critical Logic within the Core."

illustrates the connections and clock management logic required to interface

DCM

BUFG

userclk2 (125MHz)

CLK0

BUFG

userclk (62.5MHz)

CLKDV

component_name_block

(Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

gtx_clk

gmii_rx_clk

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

mdc

mdio_in

mdio_out

mdio_tri

connection