Xilinx LogiCORE IP MAC v8.5 User Manual page 28

R
Management Interface (Optional)
Table 2-4
features of the GEMAC core. See
Table 2-4: Optional Management Interface Signal Pinout
host_clk
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_rd_data[31:0]
host_miim_sel
host_req
host_miim_rdy
MAC Unicast Address (Optional)
Table 2-5
the optional Management Interface is not present.
Table 2-5: Optional MAC Unicast Address Signal Pinout
mac_unicast_address[47:0]
Note: All bits are registered on input but may be treated as asynchronous inputs.
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describes the optional signals used by the client to access the management
"Using the Optional Management Interface," on page
Signal Direction
Input
Input
Input
Input
Output
Input
Input
Output
describes the alternative method of access to the unicast address registers when
Signal
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Chapter 2: Core Architecture
Clock
Domain
n/a Clock for the Management
Interface; must be 10 MHz or
above.
host_clk Defines operation to be performed
over MDIO interface. Bit 1 is also
used as a read/write control
signal for configuration register
access.
host_clk Address of register to be accessed.
host_clk Data to write to register .
host_clk Data read from register.
host_clk When asserted, the MDIO
interface is accessed. When not
asserted, the configuration
registers are accessed.
host_clk Used to signal a transaction on the
MDIO interface.
host_clk When high, the MDIO interface
has completed any pending
transaction and is ready for a new
transaction.
Direction Description
Input Used to assess the MAC unicast
address registers when the
Management Interface is not used
1-Gigabit Ethernet MAC v8.5 User Guide
77.
Description
UG144 April 24, 2009