Figure 9-4: Timing Report Setup/Hold Illustration - Xilinx LogiCORE IP MAC v8.5 User Manual

Required Constraints
This is less than the 1 ns required, so there is slack. Equally for the –ve edge, we have
–11.179 ns of setup—this edge is at time 12 ns and therefore this equates to a setup of
0.821 ns.
The implementation requires 8.893 ns of hold to the +ve edge.
this represents 0.893 ns relative to the following rising edge of the clock (since the IDELAY
has acted to delay the clock by an entire period when measured from the input flip-flop).
This is less than the 1 ns required, so there is slack. Equally for the –ve edge, we have
12.893 ns of hold —this edge is at time 12 ns and therefore equates to a hold time of
0.893 ns.
RGMII_RXC
RGMII_RXD[3:0],
RGMII_RX_CTL
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
8.893 ns
8 ns
12 ns
12.893 ns

Figure 9-4: Timing Report Setup/Hold Illustration

www.xilinx.com
Figure 9-4
8 ns
-6.134 ns
t
SETUP
t
= 8.893 - 8
HOLD
= 0.893 ns
12 ns
-11.179 ns
t
= 12.893 - 12
HOLD
= 0.893 ns
t
R
illustrates that
= 8 - 7.179
= 0.821 ns
= 12 - 11.179
SETUP
= 0.821 ns
107