Xilinx LogiCORE IP MAC v8.5 User Manual page 100

R
Virtex-5 Devices with Delayed Clock
Setup and Hold results for the GMII input bus can be found in the data sheet section of the
Timing Report. However, depending on how the setup/hold requirements have been met,
it may not be immediately obvious how the results relate to
example for the GMII report from a Virtex-5 device where the clock has been delayed to
meet the setup/hold requirements.
The implementation requires -6.134 ns of setup.
figure of 1.866 ns relative to the following rising edge of the clock (since the IDELAY has
acted to delay the clock by an entire period when measured from the input flip-flop). This
is less than the 2 ns required, so there is slack.
100
-- DISCONTINUED PRODUCT --
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock gmii_rx_clk
------------+------------+------------+------------------+--------+
| Setup to
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase
------------+------------+------------+------------------+--------+
gmii_rx_dv | 1.955(R)|
gmii_rx_er | 1.962(R)|
gmii_rxd<0>| 1.949(R)|
gmii_rxd<1>| 1.944(R)|
gmii_rxd<2>| 1.947(R)|
gmii_rxd<3>| 1.942(R)|
gmii_rxd<4>| 1.950(R)|
gmii_rxd<5>| 1.962(R)|
gmii_rxd<6>| 1.957(R)|
gmii_rxd<7>| 1.952(R)|
------------+------------+------------+------------------+--------+
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock gmii_rx_clk
------------+------------+------------+------------------+--------+
| Setup to
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase
------------+------------+------------+------------------+--------+
gmii_rx_dv | -6.198(R)|
gmii_rx_er | -6.225(R)|
gmii_rxd<0> | -6.149(R)|
gmii_rxd<1> | -6.152(R)|
gmii_rxd<2> | -6.206(R)|
gmii_rxd<3> | -6.207(R)|
gmii_rxd<4> | -6.134(R)|
gmii_rxd<5> | -6.134(R)|
gmii_rxd<6> | -6.170(R)|
gmii_rxd<7> | -6.170(R)|
------------+------------+------------+------------------+--------+
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Chapter 9: Constraining the Core
| Hold to |
-0.017(R)| gmii_rx_clk_bufg |
-0.031(R)| gmii_rx_clk_bufg |
-0.013(R)| gmii_rx_clk_bufg |
-0.009(R)| gmii_rx_clk_bufg |
-0.012(R)| gmii_rx_clk_bufg |
-0.008(R)| gmii_rx_clk_bufg |
-0.015(R)| gmii_rx_clk_bufg |
-0.026(R)| gmii_rx_clk_bufg |
-0.022(R)| gmii_rx_clk_bufg |
-0.020(R)| gmii_rx_clk_bufg |
Figure
| Hold to |
7.526(R)| gmii_rx_clk_bufg |
7.554(R)| gmii_rx_clk_bufg |
7.484(R)| gmii_rx_clk_bufg |
7.486(R)| gmii_rx_clk_bufg |
7.532(R)| gmii_rx_clk_bufg |
7.533(R)| gmii_rx_clk_bufg |
7.476(R)| gmii_rx_clk_bufg |
7.476(R)| gmii_rx_clk_bufg |
7.506(R)| gmii_rx_clk_bufg |
7.506(R)| gmii_rx_clk_bufg |
Figure 9-2 illustrates that this represents a
1-Gigabit Ethernet MAC v8.5 User Guide
| Clock |
|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
9-1. The following is an
| Clock |
|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
0.000|
UG144 April 24, 2009