With Rgmii; Figure 10-3: Clock Management Logic With External Gmii (Multiple Cores) - Xilinx LogiCORE IP MAC v8.5 User Manual

Multiple Cores
Note:
shared between cores.
gtx_clk

With RGMII

Figure 10-4
using the optional RGMII. gtx_clk may be shared between multiple cores as illustrated,
resulting in a common transmitter clock domain across the device.
As a general rule, a common receiver clock domain is not possible. Each core receives an
independent receiver clock from the PHY attached to the other end of the RGMII—as
illustrated in
Note:
shared between cores.
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
Although not illustrated, if the optional Management Interface is used, host_clk can also be
IBUFG BUFG

Figure 10-3: Clock Management Logic with External GMII (Multiple Cores)

illustrates sharing clock resources across multiple instantiations of the core
Figure 10-4. This results in a separate receiver clock domain for each core.
Although not illustrated, if the optional Management Interface is used, host_clk can also be
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1-Gigabit Ethernet MAC
gtx_clk gmii_rx_clk
1-Gigabit Ethernet MAC
gtx_clk gmii_rx_clk
BUFG IBUFG
gmii_rx_clk1
BUFG IBUFG
gmii_rx_clk2
R
111