Keep It Registered; Recognize Timing Critical Signals; Use Supported Design Flows; Make Only Allowed Modifications - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet

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Keep it Registered

To simplify timing and increase system performance in an FPGA design, keep all inputs

and outputs registered between the user application and the core. This means that all

inputs and outputs from the user application should come from, or connect to, a flip-flop.

While registering signals may not be possible for all paths, it simplifies timing analysis and

makes it easier for the Xilinx tools to place-and-route the design.

The UCF provided with the example design identifies the critical signals and timing

constraints that should be applied. See

The core is pre-synthesized and delivered as an NGC netlist. The example implementation

scripts provided use XST 11.1 as the synthesis tool for the HDL example design. Other

synthesis tools may be used for the user application logic. The core is always unknown to

the synthesis tool and should appear as a black box. For post synthesis, only ISE® 11.1 tools

are supported.

The GEMAC core should not be modified by you. Any modifications may have adverse

effects on system timing and protocol compliance. Supported user configurations of the

GEMAC core can only be made by selecting the options in the CORE Generator when the

core is generated. See

-- DISCONTINUED PRODUCT --

Appendix C, "Calculating DCM Phase-Shifting"

Degree of Difficulty for Various Implementations

Device Family

Chapter 3, "Generating the Core."

www.xilinx.com

Chapter 4: Designing with the Core

to meet Spartan-3, Spartan-3E

Difficulty

Difficult

Easy

Chapter 9, "Constraining the Core"

1-Gigabit Ethernet MAC v8.5 User Guide

UG144 April 24, 2009

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