Xilinx LogiCORE IP MAC v8.5 User Manual page 64

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DCM Reset circuitry
A DCM reset module, not illustrated in
example design next to the DCM. Since this logic must be reliable whatever the
reset/locked status of the DCM, the module requires a reliable reference clock. In the
example design for GMII, the global transmitter clock is therefore used (gtx_clk_bufg
from
family, for the receiver DCM under the following conditions:
•
•
Spartan-3 Devices
For Spartan-3 families, the reset pulse is transferred into the DCM input clock
(gmii_rx_clk from
and routed to the reset input of the DCM.
Virtex-4 Devices
For Virtex®-4 families, the generated reset from within the DCM reset module is further
complicated. Here the DCM reset pulse duration must be asserted for a minimum of 200
ms (see the Virtex-4 Datasheet). Consequently, a 200 ms duration timer is also included in
the DCM reset module to extend the reset pulse. This reset signal is output from the DCM
reset module and should be routed to the DCM reset input port.
For Virtex-4 FPGA example designs, the reason why the 200ms input is not routed directly
to the DCM is so that simulations can occur in a timely manner.
The 200ms reset pulse takes the signal name reset_200ms in the example design HDL
files. It is routed from the DCM reset module instantiation up through all levels of
hierarchy to the top level. It is then left unconnected in the example design instantiation
from within the demonstration test bench. Furthermore, an accompanying signal,
reset_200ms_in, is routed down from the top level of the example design hierarchy to
the DCM instantiation, where it is connected to the DCM reset. From the demonstration
test bench, this reset_200ms_in signal is driven for a short duration to enable fast
simulation start up. However, to re-iterate, when implementing the design in real
hardware, the DCM reset signal must be connected correctly:
•
64
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Figure 7-1). This reset circuitry will generate an appropriate reset pulse, based on the
The locked signal from the DCM is constantly monitored. Following a high to low
transition on this signal, indicating that the DCM has lost lock, a reset will be issued.
A timeout counter is enabled when the DCM is in the loss of lock state. If, following
the timeout period, the DCM has not obtained lock, another DCM reset will be issued.
This timeout counter will time a > 1ms interval. This timeout functionality is required
for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous
clocks under certain network conditions (for example, when no ethernet cable is
connected).
Figure 7-2). Here it is extended to three DCM clock periods duration
Caution!
In the example designs for Virtex-4 families, the 200ms reset pulse from the DCM
reset module is NOT connected directly to the DCM: this signal must be connected when
implementing the core in real hardware.
This can be achieved by connecting the reset_200ms signal to the
reset_200ms_in signal at any level of example design HDL hierarchy.
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Chapter 7: Using the Physical Side Interface
Figure 7-2, is also present and is instantiated in the
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009