Functional Description; System Reset - Xilinx LogiCore PLB PCI Full Bridge Specification

PLB PCI Full Bridge (v1.00a)

System Reset

When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least
twenty clock periods of the slowest clock.
Evaluation Version
The PLB PCI Bridge is delivered with a hardware evaluation license. When programmed into a Xilinx
device, the core will function in hardware for about 8 hours at the typical frequency of operation. To use
the PLB PCI Bridge without this timeout limitation, a full license must be purchased.

Functional Description

The PLB PCI Bridge design is shown in
PLB IPIF PCI Bridge is comprised of three main modules:
• The PLB IPIF (Processor Local Bus Intellectual Property InterFace). It interfaces to the PLB bus.
• The IPIF v3.0 Bridge. It interfaces between the PLB IPIF and the v3.0 core.
• The LogiCORE PCI32 Interface v3.0 core. It interfaces to the PCI bus.
Figure Top x-ref 1
Attachment
LogiCore Version 3.0 32-bit PCI Core Requirements
The PLB PCI bridge uses the 32-bit Xilinx LogiCore Version 3 IP core. Before the bridge can perform
transactions on the PCI bus, the v3.0 core must be configured via configuration transactions from either
the PCI-side or if configuration functionality is included in the bridge configuration, from the PLB-side.
Both a design guide and an implementation guide are available for the Xilinx LogiCore v3.0 PCI IP
4
PLB IPIF
Interrupt
Module
Slave
PCI2IPIF
Master FIFO
Attachment
IPIF2PCI
FIFO
Figure 1: PLB PCI Full Bridge Block Diagram
Figure 1 and described in the following sections. As shown,
IPIF/V3 Bridge
Bridge
Registers
PCI2IPIF
FIFO
IPIF2PCI
FIFO
Master SM
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Xilinx
v3.0 PCI Core
ds508_01_112205
DS508 March 21, 2006
Product Specification